The semiconductor industry has been advanced to the field of Ultra Large Scale Integrated (ULSI) technologies. The fabrication of the metal-oxide-semiconductor transistor also follows the trend. As the size of the devices is scaled down, silicon based nanoscale electronics have been attention for these years. For example, single-electron-tunneling devices are developed in recent years. The single-electron-tunneling devices are referred to SET devices herein. As known in the art, the single-electron-tunneling devices are formed by using silicon nanocrystals and operated by so called Coulomb blockade effect. Typically, the single-electron-tunneling devices have a narrow crystalline Si channel and a nanoscal floating gate.
The Coulomb blockade effect relates to one-by-one electron manipulation, which is the basic element to operate the single-electron-tunneling devices. Since the single-electron-tunneling devices exhibit potential quantized threshold voltage shift, thus it is one of the reasons that is attracted by the researcher. In the other words, the charge of a single electron to the floating gate will lead to quantized threshold shift and discrete charging voltage. In addition, the single-electron-tunneling devices are also a very promising phenomenon for being used in extremely low power devices in the future. In order to develop the devices for commercial application, room temperature operation capabilities are necessary. Another key point of the devices is based on the Si construct. Y. Takashashi, et al. proposed a single electron transistor having conductance oscillation at room temperature. This can refer to "Conductance Oscillation of a Si Single Transistor at Room Temperature", in IEDM, Tech. Dig., p. 938, 1994. Takashashi proposed a SET device with capacitance about 2aF. Under the small capacitance, the devices exhibit conductance oscillation at room temperature. Critical steps of this method are to form a superficial silicon layer of a SIMOX (separation by implanted oxygen) wafer and perform a thermal oxidation. The oxidation occurs at the interface between the silicon and buried silicon dioxide. The oxidation occurs more in the neighborhood of the pattern edge. Therefore, the constricted regions are formed at the ends of the wire. Another prior art proposed by Nakajima disclosed the single-electron memory having an ultra-small self-aligned floating dot gate. Please see "Room Temperature Operation of Single-Electron Memory with Self-Aligned Floating Dot Gate", in IEDM Tech. Dig., p. 952, 1996.
Another article that relates to the topic is proposed by Lingjie Guo, "Si Single-Electron MOS Memory With Nanoscale Floating-Gate and Narrow Channel", in IEDM Tech. Dig., p. 955, 1996. In the article, the devices have two major features. The first one is that the width of the Si MOSFET channel is narrower than the Debye screening length of single electron, and another one is the floating gate that is in nanoscale dimension. Further, Dutta disclosed a method to make silicon nanocrystals by controlling the nucleation and growth of silicon particles in SiH.sub.4 plasma. In the prior art, the devices show Coulomb blockade and Coulomb staircase at room temperature. Specifically, the nanocrystals are formed in a very-high-frequency (VHF) plasma cell fed with SiH.sub.4 and H.sub.2 gases. Please see "Fabrication, and Electrical Characteristic of Single Electron Tunneling Devices Based on Si Quantum Dots Prepared by Plasma Processing", A. Dutta, et al., Jap. J. Appel. Phys., vol. 36, p. 4038, 1997. Although much effort has been made to realize silicon-based SET devices, their smallest dimensions required for SET operation depend on non-artificial processes, such as grain control and inhomogeneous oxidation that can hardly be determined in the design stage.